Presently, for a power semiconductor device carrying out control of high frequency and high power, a silicon (hereinafter sometimes referred to as “Si”) semiconductor is mainly used. As the band gap (forbidden band width) of the Si semiconductor, however, is merely on the order of 1.1 eV, it is not possible sometimes to use an Si semiconductor device in a high temperature environment or when exposing to radiation. As a measure against this problem, attempts have been made to use silicon carbide (hereinafter sometimes referred to as “SiC”) semiconductor having a band gap that is much wider than that of Si.
Silicon carbide is a crystalline material that is physically, chemically, and thermally stable, with a higher thermal conductivity than that of silicon. In addition, for example, the band gap of 4H—SiC as one of various polytypes is 3.25 eV, which is on the order of three times larger in comparison with 1.12 eV of Si. This makes the electric field strength causing insulation breakdown of silicon carbide (2 to 4 MV/cm) approximately one order of magnitude larger than that of silicon (0.3 MV/cm). Therefore, silicon carbide is particularly excellent as a material for a power semiconductor device that requires stability when operated at a high voltage or in a high temperature environment.
In a power semiconductor device, its on-resistance is inversely proportional to the third power of the insulation breakdown electric field strength of the material and reduces in proportion to the reciprocal of carrier mobility. Therefore, even though the carrier mobility in a silicon carbide semiconductor being lower than that of silicon semiconductor is taken into consideration, in a semiconductor substrate of silicon carbide, for example, the on-resistance thereof can be reduced to hundredths in comparison with the on-resistance of a silicon semiconductor substrate. Up to the present time, power semiconductor devices with various structures of power semiconductor devices such as diodes, transistors, and thyristors have been experimentally manufactured using silicon carbide, part of which has been already in actual use. See JP-A-2005-5428.
Meanwhile, in a power semiconductor device such as a vertical MOSFET or an IGBT using silicon as the chief material thereof, an FZ-Si wafer, for example, is used for the semiconductor substrate thereof. In this case, for reducing the contribution of a drift layer to on-resistance, the wafer is ground thinner to make the thickness of the drift layer to the minimum necessary for breakdown voltage blocking. Such a wafer thinning process technology of grinding a wafer has been developed. The thickness of the drift layer determining the breakdown voltage is determined depending on the physical property values of a semiconductor material. For example, in silicon, the thickness is approximately 70 μm for a breakdown voltage of 600V and approximately 100 μm for a breakdown voltage of 1200V.
In the development of the manufacturing process of a semiconductor device using silicon carbide, one of the goals of the development is to establish the technology of processing a thin wafer ground to the minimum necessary thickness for breakdown voltage blocking, such as a wafer with a thickness of the order of 70 μm. Thus, the establishment of the technology is progressing to a considerable extent in aspects such as an improvement in a wafer handling method for handling thin wafers. See JP-A-2005-260267.
For reducing the on-resistance of an SiC semiconductor device, JP-A-2004-22878 discloses depositing a semiconductor layer on a silicon carbide substrate before the substrate is ground to a thickness of 200 μm or less. That publication, however, discloses reducing the thickness of a semiconductor device from 400 μm to approximately 200 μm, without regards to the lower limit of the thickness of the substrate. In the first embodiment described in that publication, for manufacturing a Schottky diode, a 10 μm thick epitaxially grown layer is deposited on a silicon carbide substrate before boron ions are implanted to form a doped layer, on which an electrode is formed. When using the such manufacturing method to reduce the thickness of the substrate beyond 200 μm, such as a thickness of 100 μm or 50 μm, for example, occurrence of cracking of the substrate is predicted like in the manufacturing process of silicon. Therefore, although a semiconductor device with the thickness of the substrate being 200 μm or less is disclosed in that publication, only the manufacturing method specifically disclosed that makes the thickness of a substrate approximately 200 μm is grinding.
In a semiconductor device with silicon carbide or gallium nitride used as the chief material thereof, the margin of avalanche breakdown voltage is higher than that of a semiconductor device using silicon. Therefore, the thickness of a breakdown voltage blocking region in a MOSFET or an IGBT with the design breakdown voltage thereof being 600V to 1200V can be around 10 μm or less.
The volume resistivity of a currently available low resistance substrate of silicon carbide is higher in comparison with that of a silicon substrate. For example, in the case of silicon, a wafer having a volume resistivity less than 0.001 Ωcm is available. In contrast, in the case of silicon carbide, only a wafer having a resistivity in the range from 0.02 to 0.01 Ωcm, which is ten times or larger than the resistivity of a silicon wafer, is usable.
Moreover, when manufacturing a semiconductor device with gallium nitride used as the chief material thereof, there is difficulty in obtaining a single crystal substrate of gallium nitride. Therefore, a method is employed in which a semiconductor layer of gallium nitride is formed by hetero-epitaxial growth on a substrate of silicon carbide or sapphire.
Here, the proportion of the resistance of a silicon carbide substrate in the on-resistance of a semiconductor device will be simply obtained. The proportion will be calculated about a MOSFET manufactured by growing an epitaxial layer of silicon carbide or gallium nitride on a silicon carbide substrate with its volume resistivity being low to the currently available extent. A semiconductor layer, which becomes a MOS gate region, is epitaxially grown on the top surface of the substrate. If the silicon carbide substrate, which becomes a drain region, has a thickness approximately equal to the original thickness of 500 μm and the volume resistivity of the substrate is 0.01 Ωcm, the resistance of the substrate is calculated out as approximately 0.5 mΩcm2. Since the typical on-resistance of a MOSFET with silicon carbide used as the chief material thereof is 10 mΩcm2 at present, the proportion of the resistance of the silicon carbide substrate (drain region) in the on-resistance becomes approximately 5%. When the substrate forms the drain region or the collector region of a vertical power semiconductor device, the resistance of the substrate is to be 5% of the on-resistance in the region.
At present, most of the on-resistance of the MOSFET is channel resistance. Improvement in channel mobility makes the figure of 10 mΩcm2 expected to be a half or less. If the channel mobility is doubled, then the proportion of the resistance of a substrate in on-resistance becomes approximately 10%. Further improvement in the channel mobility will further increase the proportion of the resistance of the substrate. Thus, the reduction of the resistance of the substrate is considered to be an important issue. The volume resistivity of a currently available silicon carbide substrate, however, is on the order of 0.01 Ωcm. Reducing the volume resistivity necessitates further technological development with anticipated difficulties.
With the foregoing situation taken into consideration, also in manufacturing a vertical power semiconductor device with silicon carbide or gallium nitride used as the chief material thereof, it is considered that the establishment of the process for thinning a substrate or a wafer would become sometime indispensable for reducing the on-resistance like in the case of using silicon.
In a semiconductor device with silicon carbide or gallium nitride used as the chief material thereof, as described in the foregoing, the breakdown voltage of around 1000V can be obtained with the breakdown voltage blocking region provided as thin as approximately 10 μcm. Therefore, for the purpose of reducing on-resistance, a manufacturing method can be thought of in which a substrate of silicon carbide is made thinner like in a silicon process so as to be on the order of 10 μm thick, for example, necessary for breakdown voltage blocking. However, in an attempt to grind a semiconductor substrate or a wafer for thinning it down to on the order of 10 μcm, occurrence of defects such as cracking and chipping and production of an enormous number of particles cannot be avoided. Thus, the establishment of an excellent manufacturing process is considered to be difficult. In a silicon semiconductor device, the thickness of a breakdown voltage blocking region is 70 μcm for 600V and 100 μm for 1200V. The relatively higher thickness enables the process of thinning the entire surface of a wafer.
The present invention was developed in view of the background art and problems associated therewith. There remains a need to reduce the on-resistance of a semiconductor device having a semiconductor layer of silicon carbide or gallium nitride on a semiconductor substrate, while providing a structure that is able to retain the strength of a semiconductor substrate without cracking the wafer. The present invention addresses this need.